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Lattice Semiconductor
TXSTATUS (RO/COR)
Mnemonic: TXSTATUS
POR Value = 00H
Application Support
Name
Rsvd [7:2]
tx_fifo_full
tx_discfrm
Range
7:2
1
0
Description
Reserved.
tx_fifo_full : This bit is set high and latched if the tx_fifo_full signal from the
Loop back FIFO is asserted.
tx_discfrm : This bit is set high and latched if the tx_discfrm signal is
asserted on TSMAC IP core pin. See Table 2-1 on page 14 for more infor-
mation on this TSMAC IP core signal.
The counter registers listed in Table 5-2 are all 16 bits with 8 bit low and 8 bit high address locations. The counters
count different Rx and Tx statistics as defined by the tx_statvec and rx_statvec statistics vectors define in Table 2-1
on page 14 . All counters have a power-on reset (POR) value of 0x0000.
Table 5-2. Counter Registers
Address
0x0800c
0x0800e
0x08010
0x08012
0x08014
0x08016
0x08018
0x0801a
0x0801c
0x0801e
0x08020
0x08022
0x08024
0x08026
0x08028
0x0802a
0x0802c
0x0802e
0x08030
Register Description
RX Packet Ignored Counter Register
RX Length Check Error CouNTer
RX Long Frames CouNTer Register
RX Short Frames CouNTer Register
RX IPG violations CouNTer Register
RX CRC errors CouNTer Register
RX OK packets CouNTer Register
RX Control Frame CouNTer Register
RX Pause Frame CouNTer Register
RX Multicast Frame CouNTer Register
RX Broadcast Frame CouNTer Register
RX VLAN tagged Frame CouNTer Register
TX Unicast Frame CouNTer Register
TX Pause Frame CouNTer Register
TX Multicast Frame CouNTer Register
TX Broadcast Frame CouNTer Register
TX VLAN tagged Frame CouNTer Register
TX BAD FCS Frame CouNTer Register
TX Jumbo Frame CouNTer Register
Mnemonic
RXPICNT
RXLCECNT
RXLFCNT
RXSFCNT
RXIPGCNT
RXCRCCNT
RXOKCNT
RXCFCNT
RXPFCNT
RXMFCNT
RXBFCNT
RXVFCNT
TXUFCNT
TXPFCNT
TXMFCNT
TXBFCNT
TXVFCNT
TXBFCCNT
TXJFCNT
Type
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
(RO/COR)
IPUG51_03.0, December 2010
55
Tri-Speed Ethernet MAC User’s Guide
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